The present invention relates to a two-dimensionally arrayed solid-state imaging device having a photosensor unit comprising a photodiode matrix which is vertically scanned by a shift register and horizontally scanned by charge transfer devices.
FIG. 1 shows an example of a prior art two-dimensionally arrayed solid-state imaging device having a MOS-type photodiode array as a photosensor unit and a charge transfer device (CTD) in a horizontal scanning circuit. A similar imaging device is shown in the Preparatory Print for 1981 General Meeting of the Institute of Television Engineers of Japan, page 107.
In FIG. 1, numeral 1 denotes photodiodes, numeral 2 denotes vertical switching MOS transistors (MOST's) for addressing vertically. The photodiodes 1 and the MOST's 2 are arranged in a two-dimensional matrix. Numeral 3 denotes a vertical scanning circuit for producing a vertical address signal, numeral 4 denotes a charge transfer circuit for a horizontal scanning CTD, numeral 5 denotes a signal output circuit, numeral 6 denotes vertical signal lines, numeral 7 denotes first storage capacitors for supplying bias charges to efficiently transfer charges on the vertical signal lines 6 to the CTD, numeral 8 denotes second storage capacitors having similar functions, numeral 9 denotes third transfer gates serving as switches for isolating the vertical signal lines 6 from the first storage capacitors 7, numeral 10 denotes second transfer gates serving as switches for isolating the first storage capacitors 7 from the second storage capacitors 8, numerals 11 and 12 denote gates and drains for sweeping out quasi-signals such as vertical smears from the vertical signal lines 6, and numeral 13 denotes first transfer gates serving as switches for isolating the chrage transfer circuit 4 of the CTD from the second storage capacitor 8.
In the solid-state imaging device shown in FIG. 1, a high signal-to-noise ratio is expected due to enhanced smear suppression by sweeping out the quasi-signal such as the vertical smear to the drains 12, but it has the following problem. Since the bias charges are supplied by the first and second storage capacitors 7 and 8, the charge transfer efficiency from the vertical signal lines 6 to the first storage capacitors 7 and the charge transfer efficiency from the first storage capacitors 7 to the second storage capacitors 8 are high, but the charge transfer efficiency from the second storage capacitor 8 to the drains 12 for the quasi-signal such as vertical smears and the charge transfer efficiency from the second storage capacitors 8 to the CTD charge transfer circuit 4 for an image signal is not high because of lack of the bias charges. Particularly, when the signal charges are less under a low illumination or the smear charges are less, the charge transfer efficiency is as low as 50% or less to degrade smear suppression and decrease signal charges, with a result that the expected characteristic is hardly attained. Further, because the capacitors for supplying the internal bias are in two stages, the construction of the horizontal CTD and the MOS-type picture cell array is complex.